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stk22c48 1 this product conforms to specifications per the terms of simtek standard warranty. the product has completed simtek internal qualification testing and has reached production status. feb, 2008 document control #ml0004 rev 2.0 features ? 25, 45 ns read access & r/w cycle times ? unlimited read/write endurance ? automatic non-volatile store on power loss ? non-volatile store under hardware control ? automatic recall to sram on power up ? unlimited recall cycles ? 1 million store cycles ? 100-year non-volatile data retention ? single 5.0v + 10% operation ? commercial, industrial, and military temperatures ? 28-pin 300 mil soic or 330 mil soic (rohs- compliant) description the simtek stk22c48 is a 16kb fast static ram with a nonvolatile quantum trap storage element included with each memory cell. the sram provides the fast access & cycle times, ease of use, and unlimited read & write endurance of a normal sram. data transfers automatically to the non-volatile stor - age cells when power loss is detected (the store operation). on power-up, data is automatically restored to the sram (the recall operation). both store and recall operations are also available under software control. the simtek nvsram is the first monolithic non-vola - tile memory to offer unlimited writes and reads. it is the highest-performance, most reliable non-volatile memory available. 2kx8 autostore nvsram block diagram column i/o column dec static ram array 32 x 512 row decoder input buffers quantum trap 32 x 512 store/ recall control store recall power control a 5 a 6 a 9 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 g e w a 8 a 7 a 10 a 3 a 2 a 0 a 1 a 4 v ccx v cap hsb
2 feb, 2008 document control #ml0004 rev 2.0 stk22c48 pin configurations pin descriptions pin name i/o description a 10 -a 0 input address: the 11 address inputs select one of 2,048 bytes in the nvsram array dq 7 -dq 0 i/o data: bi-directional 8-bit data bus for accessing the nvsram e input chip enable: the active low e input selects the device w input write enable: the active low w enables data on the dq pins to be written to the address location latched by the falling edge of e g input output enable: the active low g input enables the data output buffers during read cycles. de-asserting g high caused the dq pins to tri-state. v cc power supply power: 5.0v, 10% v ss power supply ground v cap nc a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v ccx hsb a 8 a 9 nc g w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 (top) 28-pin 300 mil soic 28-pin 330 mil soic
3 stk22c48 feb, 2008 document control #ml0004 rev 2.0 voltage on input relative to ground . . . . . . . . . . . . . ?0.5v to 7.0v voltage on input relative to v ss . . . . . . . . . . ?0.6v to (v cc + 0.5v) voltage on dq 0-7 or hsb . . . . . . . . . . . . . . . . ?0.5v to (v cc + 0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . .?55 c to 125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .?65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . 15ma note a: stresses greater than those listed under ?absolute maximum rat - ings? may cause permanent damage to the device. this is a stress rating only, and functional operatio n of the device at conditions above those indicated in the operational sections of this specification is not implied. exposure to absol ute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings a dc characteristics (v cc = 5.0v 10%) e note b: i cc 1 and i cc 3 are dependent on output loading and cycle rate. the s pecified values are obtained with outputs unloaded. note c: i cc 2 and i cc 4 are the average currents required for the duration of the respective store cycles (t store ) . note d: e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. note e: v cc reference levels throughout this datasheet refer to v cc if that is where the power supply connection is made, or v cap if v cc is connected to ground. symbol parameter commercial industrial units notes min max min max i cc 1 b average v cc current 85 65 90 65 ma ma t avav = 25ns t avav = 45ns i cc 2 c average v cc current during store 3 3 ma all inputs don?t care, v cc = max i cc 3 b average v cc current at t avav = 200ns 5v, 25c, typical 10 10 ma w (v cc ? 0.2v) all others cycling, cmos levels i cc 4 c average v cap current during autostore cycle 2 2 ma all inputs don?t care i sb 1 d average v cc current (standby, cycling ttl input levels) 25 18 26 19 ma ma t avav = 25ns, e v ih t avav = 45ns, e v ih i sb 2 d v cc standby current (standby, stable cmos input levels) 1.5 1.5 ma e (v cc ? 0.2v) all others v in 0.2v or (v cc ? 0.2v) i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 5 5 a v cc = max v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.2 v cc + .5 2.2 v cc + .5 v all inputs v il input logic ?0? voltage v ss ? .5 0.8 v ss ? .5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 4ma except hsb v ol output logic ?0? voltage 0.4 0.4 v i out = 8ma except hsb v bl logic ?0? voltage on hsb output 0.4 0.4 v i out = 3ma t a operating temperature 0 70 ?40 85 c v cap storage capacitance 61 220 61 220 f 5 volt rated, 68 f+20%/-10% nom. package thermal characteristics - see website at http://www.simtek.com ac test conditions capacitance f (t a = 25 c, f = 1.0mhz) input pulse levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels. . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 symbol parameter max units conditions c in input capacitance 8 pf v = 0 to 3v c out output capacitance 7 pf v = 0 to 3v figure 1 : ac output loading 480 ohms 30 pf 255 ohms 5.0v including scope and output fixture note f: these parameters are guaranteed but not tested.
4 feb, 2008 document control #ml0004 rev 2.0 stk22c48 sram read cycles #1 & #2 (v cc = 5.0v 10%) e note g: w and hsb must be high during sram read cycles. note h: device is continuously selected with e and g both low. note i: measured 200mv from steady state output voltage. sram read cycle #1: address controlled g, h sram read cycle #2: e and g controlled g no. symbols parameter stk22c48-25 stk22c48-45 units #1, #2 alt. min max min max 1 t elqv t acs chip enable access time 25 45 ns 2 t avav g , t eleh g t rc read cycle time 25 45 ns 3 t avqv h t aa address access time 25 45 ns 4 t glqv t oe output enable to data valid 10 20 ns 5 t axqx h t oh output hold after address change 5 5 ns 6 t elqx t lz address change or chip enable to output active 5 5 ns 7 t ehqz i t hz address change or chip disable to output inactive 10 15 ns 8 t glqx t olz output enable to output active 0 0 ns 9 t ghqz i t ohz output disable to output inactive 10 15 ns 10 t elicch f t pa chip enable to power active 0 0 ns 11 t ehiccl f t ps chip disable to power standby 25 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 6 t elq x stand by data val id 4 t glqv dq (d ata o ut ) e addr ess g i cc ac tive 10 t eli cc h 11 t ehi cc l 7 t ehq z 8 t glqx 1 t el q v 9 t gh q z 2 t eleh 29 t ehax 3 t av q v 27
5 stk22c48 feb, 2008 document control #ml0004 rev 2.0 sram write cycles #1 & #2 (v cc = 5.0v 10%) e note j: if w is low when e goes low, the outputs remain in the high-impedance state. note k: e or w must be v ih during address transitions. note l: hsb must be high during sram write cycles. sram write cycle #1: w controlled k, l sram write cycle #2: e controlled k, l no. symbols parameter stk22c48-25 stk22c48-45 units #1 #2 alt. min max min max 12 t avav t avav t wc write cycle time 25 45 ns 13 t wlwh t wleh t wp write pulse width 20 30 ns 14 t elwh t eleh t cw chip enable to end of write 20 30 ns 15 t dvwh t dveh t dw data set-up to end of write 10 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 ns 20 t wlqz i, j t wz write enable to output disable 10 15 ns 21 t whqx t ow output active after end of write 5 5 ns previous data data out e address 12 t avav w 16 t whdx data in 19 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data out e address 12 t avav w data in 13 t wleh 17 t aveh data valid high impedance 14 t eleh 18 t avel 15 t dveh 19 t ehax 16 t ehdx
6 feb, 2008 document control #ml0004 rev 2.0 stk22c48 hardware mode selection note m: hsb store operation occurs only if an sram write has been done since the last nonvolatile cycle. after the store (if any) completes, the part will go into standby mode, inhibiting all operations until hsb rises. note n: i/o state assumes g < v il . activation of nonvolatile cycles does not depend on state of g . hardware store cycle (v cc = 5.0v 10%) e note o: e and g low for output behavior. note p: e and g low and w high for output behavior. note q: t recover is only applicable after t store is complete. hardware store cycle e w hsb a 12 - a 0 (hex) mode i/o power notes h x h x not selected output high z standby l h h x read sram output data active n l l h x write sram input data active x x l x nonvolatile store output high z l cc 2 m no. symbols parameter stk22c48 units notes standard alternate min max 22 t store t hlhz store cycle duration 10 ms i, o 23 t delay t hlqz time allowed to complete sram cycle 1 s i, p 24 t recover t hhqx hardware store high to inhibit off 700 ns o, q 25 t hlhx hardware store pulse width 15 ns 26 t hlbl hardware store low to store busy 300 ns data valid hsb (in) data valid 25 t hlhx 23 t delay 22 t store 24 t recover hsb (out) high impedance 26 t hlbl high impedance dq (data out)
7 stk22c48 feb, 2008 document control #ml0004 rev 2.0 autostore ?/power-up recall (v cc = 5.0v 10%) e note r: t restore starts from the time v cc rises above v switch . note s: hsb is asserted low for 1 s when v cap drops through v switch . if an sram write has not taken place since the last nonvolatile cycle, hsb will be released and no store will take place. autostore ?/power-up recall no. symbols parameter stk22c48 units notes standard alternate min max 27 t restore power-up recall duration 550 s r 28 t store t hlhz store cycle duration 10 ms p, s 29 t vsbl low voltage trigger (v switch ) to hsb low 300 ns l 30 t delay t blqz time allowed to complete sram cycle 1 s o 31 v switch low voltage trigger level 4.0 4.5 v 32 v reset low voltage reset level 3.6 v 30 t delay 29 t vsbl power-up recall brown out no store (no sram writes) no recall (v cc did not go below v reset ) brown out autostore no recall (v cc did not go below v reset ) brown out autostore recall when v cc returns above v switch autostore tm hsb w dq (data out) 28 t store 27 t restore power-up recall 31 v switch 32 v reset v cc
8 feb, 2008 document control #ml0004 rev 2.0 stk22c48 nvsram operation the stk22c48 has two separate modes of opera- tion: sram mode and nonvolatile mode. in sram mode, the memory operates as a standard fast static ram . in nonvolatile mode, data is transferred from sram to nonvolatile elements (the store opera- tion) or from nonvolatile elements to sram (the recall operation). in this mode sram functions are disabled. noise considerations the stk22c48 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cap and v ss , using leads and traces that are as short as pos- sible. as with all high-speed cmos ics, normal care- ful routing of power, ground and signals will help prevent noise problems. sram read the stk22c48 performs a read cycle whenever e and g are low and w and hsb are high. the address specified on pins a 0-10 determines which of the 2,048 data bytes will be accessed. when the read is initiated by an address transition, the out- puts will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by e or g , the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high, or w or hsb is brought low. sram write a write cycle is performed whenever e and w are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq 0-7 will be written into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. power-up recall during power up, or after any low-power condition (v cap < v reset ), an internal recall request will be latched. when v cap once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and will take t restore to complete. if the stk22c48 is in a write state at the end of power-up recall , the sram data will be corrupted. to help avoid this situation, a 10k ohm resistor should be connected either between w and system v cc or between e and system v cc . autostore mode the stk22c48 can be powered in one of three modes. during normal autostore operation, the stk22c48 will draw current from v cc to charge a capacitor con- nected to the v cap pin. this stored charge will be used by the chip to perform a single store opera- tion. after power up, when the voltage on the v cap pin drops below v switch , the part will automatically disconnect the v cap pin from v cc and initiate a store operation. figure 2 shows the proper connection of capacitors for automatic store operation. a charge storage capacitor having a capacity of between 68 f and 220 f ( 20%) rated at 6v should be provided. in system power mode, both v cc and v cap are con- nected to the + 5v power supply without the 68 f capacitor. in this mode the autostore function of the figure 2: autostore mode *if hsb is not used, it should be left unconnected. 1 16 32 31 17 68 f 6v, 20% 0.1 f bypass 30 + 10k 10k ?
9 stk22c48 feb, 2008 document control #ml0004 rev 2.0 stk22c48 will operate on the stored system charge as power goes down. the user must, however, guar- antee that v cc does not drop below 3.6v during the 10ms store cycle. autostore inhibit mode if an automatic store on power loss is not required, then v cc can be tied to ground and + 5v applied to v cap (figure 3). this is the autostore inhibit mode, in which the autostore function is disabled. if the stk22c48 is operated in this configuration, refer- ences to v cc should be changed to v cap throughout this data sheet. in this mode, store operations may be triggered with the hsb pin. to enable or disable autostore using an io port pin, see ?preventing stores? on page 9. in order to prevent unneeded store operations, automatic store s as well as those initiated by externally driving hsb low will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. if the power supply drops faster than 20 s/volt before v cc reaches v switch , then a 2.2 ohm resistor should be inserted between v cc and the system sup- ply to avoid momentary excess of current between vcc and vcap. hsb operation the stk22c48 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the stk22c48 will conditionally initiate a store operation after t delay ; an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin has a very resistive pul- lup and is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. pull up this pin with an external 10k ohm resistor to v cap if hsb is used as a driver. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the stk22c48 will continue sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. the hsb pin can be used to synchronize multiple stk22c48s while using a single larger capacitor. to operate in this mode the hsb pin should be con- nected together to the hsb pins from the other stk22c48s. an external pull-up resistor to + 5v is required since hsb acts as an open drain pull down. the v cap pins from the other stk22c48 parts can be tied together and share a single capacitor. the capacitor size must be scaled by the number of devices connected to it. when any one of the stk22c48s detects a power loss and asserts hsb , the common hsb pin will cause all parts to request a store cycle (a store will take place in those stk22c48s that have been written since the last nonvolatile cycle). during any store operation, regardless of how it was initiated, the stk22c48 will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the stk22c48 will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. preventing stores the store function can be disabled on the fly by holding hsb high with a driver capable of sourcing 30ma at a voh of at least 2.2v, as it will have to overpower the internal pull-down device that drives hsb low for 20 s at the onset of a store . when the stk22c48 is connected for autostore operation (system v cc connected to v cc and a 68 f capacitor on v cap ) and v cc crosses v switch on the way down, the stk22c48 will attempt to pull hsb low; if hsb doesn?t actually get below v il , the part will stop try- ing to pull hsb low and abort the store attempt. 17 1 16 32 31 30 bypass 0.1f 10k? 10k? figure 3: autostore inhibit mode 10k 10k
10 feb, 2008 document control #ml0004 rev 2.0 stk22c48 hardware protect the stk22c48 offers hardware protection against inadvertent store operation and sram write s dur- ing low-voltage conditions. when v cap < v switch , all externally initiated store operations and sram write s are inhibited. autostore can be completely disabled by tying v ccx to ground and applying + 5v to v cap . this is the autostore inhibit mode; in this mode store s are only initiated by explicit request using the hsb pin. low average active power the stk22c48 draws significantly less current when it is cycled at times longer than 50ns. figure 4 shows the relationship between i cc and read cycle time. worst-case current consumption is shown for both cmos and ttl input levels (commercial tem- perature range, v cc = 5.5v, 100% duty cycle on chip enable). figure 5 shows the same relationship for write cycles. if the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. the overall average current drawn by the stk22c48 depends on the following items: 1) cmos vs. ttl input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of read s to write s; 5) the operating tempera- ture; 6) the v cc level; and 7) i/o loading. figure 4: icc (max) reads 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma) figure 5: i cc (max) writes 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma)
11 stk22c48 feb, 2008 document control #ml0004 rev 2.0 best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of the product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ? the non-volatile cells in an nvsram are pro- grammed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites will sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set pro- grammed state. routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique nv pattern (e.g., complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final sys- tem manufacturing test to ensure these system routines work consistently. ? power up boot firmware routines should rewrite the nvsram into the desired state. while the nvsram is shipped in a preset state, best prac- tice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.). ? the v cap value specified in this datasheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the max v cap value because the higher inrush currents may reduce the reliability of the internal pass transistor. customers that want to use a larger v cap value to make sure there is extra store charge should discuss their v cap size selection with simtek.
12 feb, 2008 document control #ml0004 rev 2.0 stk22c48 ordering information packing option blank = tube tr = tape and reel temperature range blank = commercial (0 to 70c) i = industrial (-40 to 85c) access time 25 = 25ns 45 = 45ns lead finish f = 100% sn (matte tin) package n = plastic 28-pin 300 mil soic s = plastic 28-pin 330 mil sioc stk22c48 - n f 45 i tr
13 stk22c48 feb, 2008 document control #ml0004 rev 2.0 ordering information item number item name access times temperature stk22c48-nf25 5v 2kx 8 autostore nvsram sop28-300 25 ns access time commercial stk22c48-nf45 5v 2kx 8 autostore nvsram sop28-300 45 ns access time commercial stk22c48-sf25 5v 2kx 8 autostore nvsram sop28-330 25 ns access time commercial stk22c48-sf45 5v 2kx 8 autostore nvsram sop28-330 45 ns access time commercial STK22C48-NF25TR 5v 2kx 8 autostore nvsram sop28-300 25 ns access time commercial stk22c48-nf45tr 5v 2kx 8 autostore nvsram sop28-300 45 ns access time commercial stk22c48-sf25tr 5v 2kx 8 autostore nvsram sop28-330 25 ns access time commercial stk22c48-sf45tr 5v 2kx 8 autostore nvsram sop28-330 45 ns access time commercial stk22c48-nf25i 5v 2kx 8 autostore nvsram sop28-300 25 ns access time industrial stk22c48-nf45i 5v 2kx 8 autostore nvsram sop28-300 45 ns access time industrial stk22c48-sf25i 5v 2kx 8 autostore nvsram sop28-330 25 ns access time industrial stk22c48-sf45i 5v 2kx 8 autostore nvsram sop28-330 45 ns access time industrial stk22c48-nf25itr 5v 2kx 8 autostore nvsram sop28-300 25 ns access time industrial stk22c48-nf45itr 5v 2kx 8 autostore nvsram sop28-300 45 ns access time industrial stk22c48-sf25itr 5v 2kx 8 autostore nvsram sop28-330 25 ns access time industrial stk22c48-sf45itr 5v 2kx 8 autostore nvsram sop28-330 45 ns access time industrial
14 feb, 2008 document control #ml0004 rev 2.0 stk22c48 package diagrams 28-lead, 300 mil soic gull wing 0.009 0.23 0.013 0.32 ( ) 8 0.024 0.61 ( ) dim = inches min max dim = mm min max ( ) 0 .050 (1.27) bsc 0.292 7.42 0.300 7.59 ( ) 0.400 10.16 0.410 10.41 ( ) pin 1 index 0.014 0.35 0.019 0.48 ( ) 0.701 17.81 0.711 18.06 ( ) 0.090 2.29 0.094 2.39 ( ) 0.097 2.46 0.104 2.64 ( ) ( ) 0.005 0.12 0.012 0.29
15 stk22c48 feb, 2008 document control #ml0004 rev 2.0 28-lead, 330 mil soic gull wing dim = inches min max dim = mm min max ( ) pin 1 0.477 0.453 12.116 11.506 ( ) 0.336 0.326 8.534 8.280 ( ) 0.044 0.028 1.117 0.711 ( ) 10 0 0.014 0.008 0.356 0.203 ( ) 0.103 0.093 2.616 2.362 ( ) 0.112 (2.845) 0.004 (0.102) 0.713 0.733 18.11 18.62 ( ) 0.020 0.014 0.508 0.356 ( ) 0.050 (1.270)
16 feb, 2008 document control #ml0004 rev 2.0 stk22c48 document revision history simtek stk22c48 datasheet, january 2008 copyright 2008, simtek corporation. all rights reserved. this datasheet may only be printed for the expressed use of simtek customers. no part of the datasheet may be reproduced in any other form or means without the express written permission from simtek corporation. the information contained in this publication is believed to be accurate, but changes may be made without notice. simtek does not assume responsibility for, or grant or imply any warranty, in cluding mer - chantability or fitness for a particular p urpose regarding this information, the prod uct or its use. nothing herein constitutes a license, grant or transfer of any rights to any simtek patent, copyright, trademark, or other proprietary right. revision date summary 0.0 december 2002 removed 20 nsec device. 0.1 september 2003 added lead-free lead finish 0.2 march 2006 obsolete: 35ns speed grade, plastic dip packages and leaded lead finish 0.3 february 2007 add fast power-down sl ew rate information add tape reel ordering options add product ordering code listing add package drawings reformat entire document 2.0 january 2008 in the block diagram and elsewhere in this data sheet, removed the ?x? from v ccx . page 4: in sram read cycles #1 & #2 table, revised description for t elqx and t ehqz and changed symbol #2 to t eleh for read cycle time. page 4: updated sram read cycle #2 timing diagram and changed title to add g controlled. page 9: under hsb operation, revised first paragraph to read ?the hsb pin has a very resistive pullup...? page 11: added best practices section. page 13: added access times to ordering information table.

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